OpenBCM V1.07b12 (Linux)

Packet Radio Mailbox

SR1BSZ

[Szczecin_PL JO73GK]

 Login: GUEST





  
G8MNY  > TECH     28.02.24 09:56z 58 Lines 2639 Bytes #-2040 (0) @ WW
BID : 2351_GB7CIP
Read: GUEST
Subj: Locking a Frequency with 555
Path: SR1BSZ<IW0QNL<HB9ON<IW8PGT<LU4ECL<GB7CIP
Sent: 240228/0958Z @:GB7CIP.#32.GBR.EURO #:2351 [Caterham Surrey GBR] $:2351_GB
From: G8MNY@GB7CIP.#32.GBR.EURO
To  : TECH@WW

By G8MNY                            (Updated Jan 16)
(8 Bit ASCII graphics use code page 437 or 850, Terminal Font)

Years ago I had a valve B&W 405 line camera that used many double triode
astables to lock the 50Hz frame timebase to line interlaced 11250Hz line
frequency! I reworked it for 625 line by raising the 2x line LC osc to 31250Hz
& locking 4x 1/5 the frequency astables to it (>6250>1250>250>50Hz) to
correctly lock the interlaced frame timebase all done in valves!

The other day I had a similar problem, to lock an old 1980s stereo coder design
to a modern RDS unit. This is normally done the other way around, locking RDS
data unit from the 19kHz pilot! The trouble with my approach was there was no
clean 57kHz to start with! The Pic RDS generator had 6 data bits added to
synthesise the QPSK sine waves etc. So I used the MSB data line to give the
best 57kHz starting clock.

                     +15VÄÄÄÄÄÂÄÄÄÄÄÄ4k7
                              ³     Preset
                              ³8      ³
                           ÚÄÄÁÄÄÄ¿7  1k
        Ú¿Ú¿               ³ +ve dÃÄÄÄ´ R    ÚÄÄ¿
         ³³³               ³      ³6 10k     ³
Very     ÀÙÀ  /\/\/        ³LM  thÃÄÄÄ´   ³  ³
Jittery                    ³555   ³2  ³   ³  ³    /\  /\
57kHz  >ÄÄ33kÄÄÂÄÄÄÄ¿      ³     tÃÄÄÄ´   ÀÄÄÙ      \/
5V Square      ³  Lock    5³      ³3  ³ u1                     Jittery 19kHz
wave          ===  Pot<Ä´ÃÄ´CV   oÃÄÄÄ)Ä´ÃÄÄÄÄ10kÄÄÄÂÄÄÄÄ33kÄÄ>Ramp To Gently
            1n ³   4k7  u1 ÀÄÄÂÄÄÄÙ   ³             ³          Lock a Wayne
               ³    ³        1³     C===3n3        ===2n7      Sine wave Osc
        ÄÄÄÄÄÄÄÁÄÄÄÄÁÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄ

I found a slightly less jittery lock was obtained when both square waves were
ramped to a triangle with a CR. The 555 19kHz astable is loosely locked to the
57kHz by modulating the Control Voltage rail used to compare the CR voltage.

The smaller the lock input the more loosely locked (higher Q) result, but less
stable to temp/Voltage changes. The C & R 555 components that set the 19kHz
need to be high stability types!

Result, after getting the ramps right & enough lock drive to the 555 astable @
19kHz, it reliably locks up hot & cold, & with Wayne bridge sine osc gives a
stable locked osc in the right phase too in my application!


The above principle can be used for up & down locking of different frequencies
in many fractions etc. e.g. 50Hz from 60Hz.


See tech buls "Off Air Lock for Ref Osc.", & "Simple 1kHz AF Test Osc".


Why don't U send an interesting bul.

73 De John, G8MNY @ GB7CIP


Read previous mail | Read next mail


 28.03.2030 13:15:33zGo back Go up